• 专利附录
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  • 权利要求
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    • 专利摘要:
    Disclosed is a semiconductor memory device capable of generating test write data using only a system clock without using a data input / output pin of a tester. The semiconductor memory device of the present invention includes a clock delay unit that receives a system clock and generates a delay data signal in response to a control signal, and at least one of which is enabled or disabled by the system clock and receives the delay data signal to generate internal data. And a data receiving unit. Since the data input / output pin of the tester is not used by the semiconductor memory device of the present invention, the test cost can be reduced.
    公开号:KR20020031495A
    申请号:KR1020000061990
    申请日:2000-10-20
    公开日:2002-05-02
    发明作者:이형용
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Semiconductor memory device using system clock as writing data for test}
    [8] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a system clock as write data.
    [9] In general, in order to perform a write operation on a semiconductor memory device, a data input / output pad to which write data is directly input from the outside and a data receiver circuit connected to the pad are required. In addition, a system clock signal is required for the data receiver circuit to be driven in synchronization with the system. At this time, if the electrical test is performed in the mass production process for the semiconductor memory device having such a configuration, the test write and read operations are performed by using the data input / output pins of the tester to correspond to the number of data input / output pads of the semiconductor memory device. Should be.
    [10] 1 is a diagram showing a data receiving unit in a conventional write operation.
    [11] The conventional data receiver 100 shown in FIG. 1 is enabled or disabled by the system clock SCLK and receives the external data signal EDS to generate the internal data DIN. Since the external data signal (EDS) is directly received through the data input / output pads, the number of data input / output pins of the tester is used for the test.
    [12] 2 is a timing diagram illustrating an operation of a conventional data receiver.
    [13] The timing diagram of FIG. 2 is a case where the semiconductor memory device including the data receiver of FIG. 1 is a dual data rate dynamic random access memory (DDR DRAM). That is, in FIG. 1, the data receiver driven at the falling edge of the system clock SCLK is omitted.
    [14] 1 and 2, the external data signal EDS input from the data input / output pad is an 8-bit signal having a format of 10101010, and the data receiver 100 is driven at the rising edge and the falling edge of the system clock SCLK. do.
    [15] However, the conventional data receiver 100 shown in FIG. 1 requires the input of an external data signal EDS through the data input / output pad in order to perform the test write operation. I / O pins are required, which is directly related to the cost of the test. To reduce test costs, the number of data input and output pins on the test equipment is needed. To this end, various methods such as merging data input / output pads are used. However, there is a problem inherently using the data input / output pins of the test equipment.
    [16] An object of the present invention is to provide a semiconductor memory device in which write data can be input without using data input / output pins of a tester.
    [17] Another object of the present invention is to provide a semiconductor memory device capable of selectively using external data passing through a system clock or data input / output pad as test write data.
    [1] BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.
    [2] 1 is a diagram showing a data receiving unit in a conventional write operation.
    [3] 2 is a timing diagram illustrating an operation of a conventional data receiver.
    [4] 3 is a diagram illustrating a semiconductor memory device using a system clock as test write data according to an exemplary embodiment of the present invention.
    [5] 4 is a diagram illustrating a clock delay unit illustrated in FIG. 3.
    [6] FIG. 5 is a timing diagram illustrating an operation of a data receiver of a semiconductor memory device in accordance with an embodiment of the present invention illustrated in FIG. 3.
    [7] FIG. 6 illustrates a semiconductor memory device capable of selectively using external data that has passed through a system clock or data input / output pad according to an embodiment of the present invention as test write data.
    [18] According to an aspect of the present invention, a clock delay unit for receiving a system clock and generating a delay data signal in response to a control signal, and enabled or disabled by the system clock, receives the delay data signal. There is provided a semiconductor memory device comprising at least one data receiving unit for generating internal data. The clock delay unit delays selecting at least one delay circuit for receiving the system clock and one or more of the delay circuits in response to the control signal when there are two or more delay circuits, and generating the selected delay circuit signal as the delay data signal. A circuit selector is provided.
    [19] According to another aspect of the present invention, a clock delay unit for receiving a system clock and generating a delay data signal in response to a control signal, and an external device through the delay data signal and a data input / output pad in response to the control signal. An input selector that receives and selects a data signal and generates the selected signal as an input select signal, and at least one data receiver that is enabled or disabled by the system clock and receives the input select signal to generate internal data; There is provided a semiconductor memory device characterized in that.
    [20] DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.
    [21] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.
    [22] 3 is a diagram illustrating a semiconductor memory device using a system clock as test write data according to an exemplary embodiment of the present invention.
    [23] Referring to FIG. 3, a semiconductor memory device according to an embodiment of the present invention receives a system clock SCLK and generates a clock delay unit 350 that generates a delay data signal DCLK in response to a control signal SCTRL. At least one data receiver 300 or 310 is enabled or disabled by the clock SCLK and receives the delayed data signal DCLK to generate internal data DIN.
    [24] Hereinafter, an operation of the semiconductor memory device according to the embodiment of the present invention will be described in detail with reference to FIG. 3.
    [25] The system clock SCLK is applied to the clock delay unit 350 and the at least one data receiver 300 and 310. The clock delay unit 350 includes at least one delay circuit 410 and 420 and a delay circuit selector 450 as shown in FIG. 4. The clock delay unit 350 is described in detail in FIG. 4 described later. The system clock SCLK applied to the clock delay unit 350 is generated as a delay data signal DCLK by the delay circuit selector 450 controlled by the delay circuits 410 and 420 and the control signal SCTRL.
    [26] The data receivers 300 and 310 are enabled or disabled by the system clock SCLK, and receive the delay data signal DCLK to generate internal data DIN. In FIG. 3, the data receivers 300 and 310 are shown as D-flip flops. That is, the delay data signal DCLK is received at the rising or falling edge of the system clock SCLK and generated as internal data DIN at the next edge of the system clock SCLK. The data receivers 300 and 310 may be provided in plural numbers, and each of the data receivers 300 and 310 receives the delayed data signal DCLK generated by the clock delay unit 350 in common.
    [27] 4 is a diagram illustrating a clock delay unit illustrated in FIG. 3.
    [28] Referring to FIG. 4, when at least one delay circuit 410 and 420 and the delay circuits 410 and 420 which receive the system clock SCLK and generate the delay circuit signals DS1 and DS2 are included in the clock delay unit 400. A delay circuit selector 450 for selecting one of the delay circuit signals DS1 and DS2 in response to the control signal SCTRL and generating the selected delay circuit signals DS1 and DS2 as the delay data signal DCLK. .
    [29] Hereinafter, the operation of the clock delay unit 400 will be described in detail with reference to FIG. 4.
    [30] At least one delay circuit 410 and 420 in the clock delay unit 400 receives the system clock SCLK and generates delay circuit signals DS1 and DS2. Although the delay circuits 410 and 420 illustrated in FIG. 4 are configured only with buffers, the delay circuits 410 and 420 may be provided as circuits capable of delaying the system clock SCLK to obtain various data formats. That is, the delay circuits 410 and 420 may be configured in plural numbers by varying the number of buffers, and a circuit such as a frequency multiplier may be used.
    [31] The delay circuit selector 450 selects one of the delay circuit signals DS1 and DS2 in response to the control signal SCTRL when the delay circuits 410 and 420 are two or more, and delays the selected delay circuit signals DS1 and DS2. It occurs as a signal DCLK. The delay circuit selector 450 selects one of the plurality of delay circuit signals DS1 and DS2 in response to the control signal SCTRL and thus may be configured as a multiplex. In addition, the delay circuit selector 450 may be configured by using a plurality of transfer gates. That is, since the delay circuit selector 450 has a function of multiplexing and the configuration and operation of such a circuit are obvious to those skilled in the art, detailed description thereof will be omitted herein.
    [32] The control signal SCTRL is applied to the delay circuit selector 450 to control the delay circuit selector 450 so that one of the delay circuit signals DS1 and DS2 is selected when the write operation mode of the system clock SCLK is selected. do. Since the selection method of the write operation mode of the semiconductor memory device is apparent to those skilled in the art, detailed descriptions thereof are omitted herein.
    [33] FIG. 5 is a timing diagram illustrating an operation of a data receiver of a semiconductor memory device in accordance with an embodiment of the present invention illustrated in FIG. 3. The system clock SCLK passes through the delay circuit 410 of FIG. 4 and is output as an 8-bit delay data signal DCLK having a format of 10101010. Therefore, if the system clock SCLK is selected through the delay circuit 420 of FIG. 4, it will be output as an 8-bit delay data signal DCLK having a format of 01010101. In this manner, various types of delay data signals DCLK may be generated, and test write operations may be performed without using a data pin of the tester.
    [34] FIG. 6 illustrates a semiconductor memory device capable of selectively using external data passing through a system clock or a data input / output pad according to an embodiment of the present invention as test write data.
    [35] Referring to FIG. 6, a semiconductor memory device according to an exemplary embodiment of the present invention receives a system clock SCLK and controls a clock delay unit 650 that generates a delay data signal DCLK in response to a control signal SCTRL. The input selector 620 and the system for receiving and selecting the delay data signal DCLK and the external data signal EDS through the data input / output pad in response to the signal SCTRL and generating the selected signal as the input selection signal IDS. At least one data receiver 600 or 610 is enabled or disabled by the clock SCLK and receives the input selection signal IDS to generate internal data DIN.
    [36] Hereinafter, an operation of the semiconductor memory device according to the embodiment of the present invention will be described in detail with reference to FIG. 6.
    [37] The system clock SCLK is applied to the clock delay unit 650 and at least one data receiver 600 and 610. The clock delay unit 650 has the same configuration as that illustrated in FIG. 4. Therefore, detailed description of the configuration and operation is omitted. The system clock SCLK applied to the clock delay unit 650 is transferred to the delay data signal DCLK by a delay circuit selector (not shown) controlled by an internal delay circuit (not shown) and a control signal SCTRL. Is generated.
    [38] The input selector 620 receives the delay data signal DCLK and the external data signal EDS to generate the input selection signal IDS. The external data signal EDS is write data for a test transmitted from the data input / output pin of the tester through the data input / output pad of the semiconductor memory device. The input selector 620 selects one of the delay data signal DCLK and the external data signal EDS by the control signal SCTRL. When the delay circuit selector (not shown) is disabled by the control signal SCTRL applied to the clock delay unit 650, the input selector 620 selects the external data signal EDS. When the delay data signal DCLK is generated in the delay circuit selector (not shown) by the control signal SCTRL, the input selector 620 selects the delay data signal DCLK instead of the external data signal EDS. The control signal SCTRL is adjusted in accordance with the selection of the write operation mode of the system clock SCLK. Since the selection method of the write operation mode of the semiconductor memory device is apparent to those skilled in the art, detailed description thereof is omitted herein.
    [39] The data receivers 600 and 610 are enabled or disabled by the system clock SCLK, and receive the input selection signal IDS to generate internal data DIN. In FIG. 6, the data receivers 600 and 610 are illustrated as D-flip flops. That is, the input selection signal IDS is received at the rising edge or the falling edge of the system clock SCLK and is generated as internal data DIN at the next edge of the system clock SCLK. The data receivers 600 and 610 may be provided in plurality, and each of the data receivers 600 and 610 may receive the input selection signal IDS generated by the input selector 620 in common.
    [40] As described above, the semiconductor memory device according to the present invention can selectively use external data passing through the system clock or data input / output pad as test write data.
    [41] As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
    [42] As described above, the semiconductor memory device according to the present invention generates test write data only by the system clock itself without using the data input / output pins of the tester, or optionally, by using the data input / output pins of the tester or by itself. By generating test write data and testing the semiconductor memory device, the test cost can be reduced.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] A clock delay unit receiving a system clock and generating a delay data signal in response to a control signal; And
    And at least one data receiving unit enabled or disabled by the system clock and receiving the delayed data signal to generate internal data.
    [2" claim-type="Currently amended] The method of claim 1, wherein the clock delay unit
    At least one delay circuit for receiving the system clock and generating a delay circuit signal; And
    And a delay circuit selector for selecting one of the delay circuit signals in response to the control signal and generating the selected delay circuit signal as the delay data signal when there are two or more delay circuits.
    [3" claim-type="Currently amended] A clock delay unit receiving a system clock and generating a delay data signal in response to a control signal;
    An input selector which receives and selects the delay data signal and an external data signal through a data input / output pad in response to the control signal and generates the selected signal as an input selection signal; And
    And at least one data receiver configured to be enabled or disabled by the system clock and to receive the input selection signal to generate internal data.
    [4" claim-type="Currently amended] The clock delay unit of claim 3, wherein the clock delay unit
    At least one delay circuit for receiving the system clock and generating a delay circuit signal; And
    And a delay circuit selector for selecting one of the delay circuit signals in response to the control signal and generating the selected delay circuit signal as the delay data signal when there are two or more delay circuits.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-10-20|Application filed by 윤종용, 삼성전자 주식회사
    2000-10-20|Priority to KR1020000061990A
    2002-05-02|Publication of KR20020031495A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000061990A|KR20020031495A|2000-10-20|2000-10-20|Semiconductor memory device using system clock as writing data for test|
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